-- ***************************************************************************** -- maple_rd.vhd -- -- 2002-xx-xx -- ***************************************************************************** library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity maple_rd is port( CLK :in std_logic; -- 24MHz Resetn :in std_logic; Maple_A_in :in std_logic; Maple_B_in :in std_logic; Pic_Data :out std_logic_vector(7 downto 0) -- Pic_RE :in std_logic; -- Pic_Timer_Int :in std_logic; -- Pld_RD_End :out std_logic ); end maple_rd; architecture maple_rd of maple_rd is signal Maple_A :std_logic; signal Maple_B :std_logic; signal Sel_Logic :std_logic; signal Header_MB_tmp1 :std_logic; signal Header_MB_tmp2 :std_logic; signal Header_MB :std_logic; signal Header_MB_Count :std_logic_vector(2 downto 0); signal Header_Phase :std_logic; signal Data_MA_WE_tmp1 :std_logic; signal Data_MA_WE_tmp2 :std_logic; signal Data_MA_WE :std_logic; signal Data_MB_WE_tmp1 :std_logic; signal Data_MB_WE_tmp2 :std_logic; signal Data_MB_WE :std_logic; signal Data_Phase :std_logic; signal Maple_A_Data_FF1 :std_logic; signal Maple_A_Data_FF2 :std_logic; signal Maple_A_Data_FF3 :std_logic; signal Maple_A_Data_FF4 :std_logic; signal Maple_B_Data_FF1 :std_logic; signal Maple_B_Data_FF2 :std_logic; signal Maple_B_Data_FF3 :std_logic; signal Maple_B_Data_FF4 :std_logic; signal Maple_bit_Count :std_logic_vector(3 downto 0); signal Maple_Data :std_logic_vector(7 downto 0); signal Data_MB_WE_FF1 :std_logic; begin Header_Phase <= '0'; process (CLK, Resetn) begin if (Resetn = '0') then Maple_A <= '1'; Maple_B <= '1'; elsif (CLK'event and CLK = '1') then Maple_A <= Maple_A_in; Maple_B <= Maple_B_in; end if; end process; process (CLK, Resetn) begin if (Resetn = '0') then Sel_Logic <= '0'; elsif (CLK'event and CLK = '1') then if (Header_Phase = '1') then Sel_Logic <= '0'; elsif (Data_Phase = '1') then Sel_Logic <= '1'; end if; end if; end process; process (CLK, Resetn) begin if (Resetn = '0') then Header_MB_tmp1 <= '0'; elsif (CLK'event and CLK = '1') then if (Sel_Logic = '0') then if (Maple_B = '0') then Header_MB_tmp1 <= '1'; else Header_MB_tmp1 <= '0'; end if; else Header_MB_tmp1 <= '0'; end if; end if; end process; process (CLK, Resetn) begin if (Resetn = '0') then Header_MB_tmp2 <= '0'; elsif (CLK'event and CLK = '1') then if (Sel_Logic = '0') then Header_MB_tmp2 <= Header_MB_tmp1; else Header_MB_tmp2 <= '0'; end if; end if; end process; Header_MB <= Header_MB_tmp1 and (not Header_MB_tmp2); process (CLK, Resetn) begin if (Resetn = '0') then Header_MB_Count <= (others => '0'); elsif (CLK'event and CLK = '1') then if (Sel_Logic = '0') then if (Header_MB = '1') then if (Maple_A = '0') then Header_MB_Count <= Header_MB_Count + 1; else Header_MB_Count <= (others => '0'); end if; end if; end if; end if; end process; process (CLK, Resetn) begin if (Resetn = '1') then Data_Phase <= '0'; elsif (CLK'event and CLK = '1') then if (Header_MB_Count = 4) then Data_Phase <= '1'; elsif (Sel_Logic = '1') then Data_Phase <= '0'; end if; end if; end process; process (CLK, Resetn) begin if (Resetn = '1') then Data_MA_WE_tmp1 <= '0'; elsif (CLK'event and CLK = '1') then if (Data_Phase = '1') then if (Maple_B = '0') then Data_MA_WE_tmp1 <= '1'; else Data_MA_WE_tmp1 <= '0'; end if; else Data_MA_WE_tmp1 <= '0'; end if; end if; end process; process (CLK, Resetn) begin if (Resetn = '1') then Data_MA_WE_tmp2 <= '0'; elsif (CLK'event and CLK = '1') then if (Data_Phase = '1') then Data_MA_WE_tmp2 <= Data_MA_WE_tmp1; else Data_MA_WE_tmp2 <= '0'; end if; end if; end process; Data_MA_WE <= Data_MA_WE_tmp1 and (not Data_MA_WE_tmp2); process (CLK, Resetn) begin if (Resetn = '1') then Data_MB_WE_tmp1 <= '0'; elsif (CLK'event and CLK = '1') then if (Data_Phase = '1') then if (Maple_A = '0') then Data_MB_WE_tmp1 <= '1'; else Data_MB_WE_tmp1 <= '0'; end if; else Data_MB_WE_tmp1 <= '0'; end if; end if; end process; process (CLK, Resetn) begin if (Resetn = '1') then Data_MB_WE_tmp2 <= '0'; elsif (CLK'event and CLK = '1') then if (Data_Phase = '1') then Data_MB_WE_tmp2 <= Data_MB_WE_tmp1; else Data_MB_WE_tmp2 <= '0'; end if; end if; end process; Data_MB_WE <= Data_MB_WE_tmp1 and (not Data_MB_WE_tmp2); process (CLK, Resetn) begin if (Resetn = '1') then Maple_A_Data_FF1 <= '0'; elsif (CLK'event and CLK = '1') then if (Data_MA_WE = '1') then Maple_A_Data_FF1 <= Maple_A; end if; end if; end process; process (CLK, Resetn) begin if (Resetn = '1') then Maple_A_Data_FF2 <= '0'; elsif (CLK'event and CLK = '1') then if (Data_MA_WE = '1') then Maple_A_Data_FF2 <= Maple_A_Data_FF1; end if; end if; end process; process (CLK, Resetn) begin if (Resetn = '1') then Maple_A_Data_FF3 <= '0'; elsif (CLK'event and CLK = '1') then if (Data_MA_WE = '1') then Maple_A_Data_FF3 <= Maple_A_Data_FF2; end if; end if; end process; process (CLK, Resetn) begin if (Resetn = '1') then Maple_A_Data_FF4 <= '0'; elsif (CLK'event and CLK = '1') then if (Data_MA_WE = '1') then Maple_A_Data_FF4 <= Maple_A_Data_FF3; end if; end if; end process; process (CLK, Resetn) begin if (Resetn = '1') then Maple_B_Data_FF1 <= '0'; elsif (CLK'event and CLK = '1') then if (Data_MB_WE = '1') then Maple_B_Data_FF1 <= Maple_B; end if; end if; end process; process (CLK, Resetn) begin if (Resetn = '1') then Maple_B_Data_FF2 <= '0'; elsif (CLK'event and CLK = '1') then if (Data_MB_WE = '1') then Maple_B_Data_FF2 <= Maple_B_Data_FF1; end if; end if; end process; process (CLK, Resetn) begin if (Resetn = '1') then Maple_B_Data_FF3 <= '0'; elsif (CLK'event and CLK = '1') then if (Data_MB_WE = '1') then Maple_B_Data_FF3 <= Maple_B_Data_FF2; end if; end if; end process; process (CLK, Resetn) begin if (Resetn = '1') then Maple_B_Data_FF4 <= '0'; elsif (CLK'event and CLK = '1') then if (Data_MB_WE = '1') then Maple_B_Data_FF4 <= Maple_B_Data_FF3; end if; end if; end process; process (CLK, Resetn) begin if (Resetn = '1') then Maple_bit_Count <= (others => '1'); elsif (CLK'event and CLK = '1') then if (Sel_Logic = '1') then if (Data_MA_WE = '1' or Data_MB_WE = '1') then if (Maple_bit_Count = 7) then Maple_bit_Count <= (others => '0'); else Maple_bit_Count <= Maple_bit_Count + 1; end if; end if; else Maple_bit_Count <= (others => '1'); end if; end if; end process; process (CLK, Resetn) begin if (Resetn = '1') then Data_MB_WE_FF1 <= '0'; elsif (CLK'event and CLK = '1') then Data_MB_WE_FF1 <= Data_MB_WE; end if; end process; process (CLK, Resetn) begin if (Resetn = '1') then Maple_Data <= (others => '0'); elsif (CLK'event and CLK = '1') then if (Data_MB_WE_ff1 = '1' and Maple_bit_Count = 7) then Maple_Data <= Maple_B_Data_FF4 & Maple_A_Data_FF4 & Maple_B_Data_FF3 & Maple_A_Data_FF3 & Maple_B_Data_FF2 & Maple_A_Data_FF2 & Maple_B_Data_FF1 & Maple_A_Data_FF1; end if; end if; end process; Pic_Data <= Maple_Data; end maple_rd;